There are several interrelated design parameters that must be considered during SRAM cell design. These include, static noise margin (hereinafter “SNM”), write margin, bit line speed, and data retention voltage. SNM is defined as the minimum DC noise voltage necessary to flip the state of the SRAM cell. An SRAM cell can have different SNM during read and write operations, referred to as read SNM and write SNM, respectively. Read SNM is also an indicator of cell stability and is sometimes simply referred to as cell stability. A higher read SNM indicates that it is more difficult to invert the state of the cell during a read operation. Write margin is defined as the minimum bit line voltage necessary to invert the state of an SRAM cell. A higher write margin indicates that it is easier to invert the state of the cell during a write operation. Read speed is defined as the bit line slew rate in response to a high word line voltage, typically the time from the rising edge assertion of word line until some differential between the high and falling bit line is obtained. Data retention voltage is defined as the minimum power supply voltage required to retain a logic value in the SRAM cell in standby mode.
As process technology has scaled, it has become increasingly difficult to control the variation of transistor parameters because of a variety of factors, including, for example, Random Dopant Fluctuation (RDF). Other reasons for this variation include dopant scattering effect, such as the well proximity effect, that makes the placement of dopants in MOSFET transistors increasingly difficult as transistor size is reduced. Misplaced dopants can reduce transistor performance, increase transistor variability, including variability of channel transconductance, capacitance effects, threshold voltage, and leakage. Such variability increases as transistors are reduced in size, with each misplaced dopant atom having a greater relative effect on transistor properties, as a result of the overall reduction in the number of dopant atoms.
In part because of such random variations, threshold voltage variations have become a limiting factor in transistor design as process technology is scaled downward. The resulting threshold voltage variations between neighboring MOSFETs can have significant impact on the SNM, cell stability, write margin, read speed, and data retention voltage of the SRAM cell. For example, threshold voltage variations between pass-gate and pull-down transistors of the SRAM cell can significantly degrade cell stability. During a read, the read current discharging the bit line flows through the series connection of the pass-gate and pull-down NMOS transistors. The voltage divider formed by these transistors raises the low voltage in the cell, and may unintentionally cause the cell to flip when read. Variations in the threshold voltage of the pass-gate or pull-down transistor can result in a large variation in the voltage divider ratio of the pass-gate transistors and the pull down transistors, increasing the likelihood of inverting the SRAM cell during a read operation, i.e., upsetting the stored state. Other SRAM cell design parameters such as write margin, bit line speed (as measured by slew rate) or read current, and data retention voltage can also be affected by threshold voltage variations.
Attempts have been made to correct the adverse effect of threshold voltage variations on SRAM cell performance. For example, U.S. Pat. No. 7,934,181 titled, “Method and Apparatus for Improving SRAM Cell Stability by Using Boosted Word Lines”, assigned to International Business Machines Corporation, sets out a boost voltage generator that applies a predetermined boosted word line voltage to the word line of a selected SRAM cell. The boosted word line voltage is predetermined for each SRAM cell, and is sufficiently higher than the power supply voltage of the SRAM cell to improve the cell stability to a desired level.
Alternatively, US Patent Publication 20100027322 titled, “Semiconductor Integrated Circuit and Manufacturing Method Therefor”, assigned to Renesas Technology Corp., sets out measuring the threshold voltages of PMOS and NMOS transistors of the SRAM, programming control information in control memories that are associated with PMOS and NMOS transistors based on the measurements, and adjusting the levels of the body bias voltages applied to the PMOS and NMOS transistors of the SRAM to compensate for the threshold voltage variations and improve manufacturing yield.